module utm(psw, lsg, sa, clk, rxd, txd);
  input[3:0]    psw;
  output[7:0]   lsg;
  output[5:0]   sa;
  input         clk,rxd;  
  output        txd;

  wire      clk19,clk15;
  wire[3:0] keypush,keyon;

  wire[3:0] led5,led4,led3,led2,led1,led0;

  clk_diviser g_cd(clk19,clk15,clk);
  keyin g_keyin(keypush, keyon, psw, clk19, clk);

  tm g_tm(led5,led4,led3,led2,led1,led0,keypush,keyon,clk19,clk,rxd,txd);
  showtm g_stm(sa,lsg,clk,clk15, led5,led4,led3,led2,led1,led0);
endmodule

// original clock : 18.432MHz
// clk15: 18.432MHz/ 2^15 = 562Hz
// clk19: 18.432MHz/ 2^19 = 34Hz
module clk_diviser( clk19, clk15, clk);
  output    clk19,clk15;
  input     clk;

  reg[18:0] clkff;

  always @(posedge clk)
    clkff = clkff + 1;

  assign    clk15 = clkff[14];
  assign    clk19 = clkff[18];
endmodule


module keyin(keypush, keyon, psw, clkkey, clk);
  output[3:0]   keypush,keyon;
  reg[3:0]      keypush;
  reg[3:0]      keyon;
  input[3:0]    psw;
  input         clk,clkkey;

  reg[3:0]      ffa, ffb, ffc;

  always @(posedge clkkey)
  begin
    ffa <= psw;
    ffb <= ffa;
  end
  always @(posedge clk)
  begin
    ffc <= ffb;
    if(ffc[0]==1 && ffb[0]==0 && ffa[0]==0) keypush[0]=1; else keypush[0]=0;
    if(ffc[1]==1 && ffb[1]==0 && ffa[1]==0) keypush[1]=1; else keypush[1]=0;
    if(ffc[2]==1 && ffb[2]==0 && ffa[2]==0) keypush[2]=1; else keypush[2]=0;
    if(ffc[3]==1 && ffb[3]==0 && ffa[3]==0) keypush[3]=1; else keypush[3]=0;
    
    if(ffb[0]==0 && ffa[0]==0)  keyon[0]=1;   else keyon[0]=0;
    if(ffb[1]==0 && ffa[1]==0)  keyon[1]=1;   else keyon[1]=0;
    if(ffb[2]==0 && ffa[2]==0)  keyon[2]=1;   else keyon[2]=0;
    if(ffb[3]==0 && ffa[3]==0)  keyon[3]=1;   else keyon[3]=0;
    
  end
endmodule


/* Dynamic 7seg */

module dynamic_7seg(sa, lsg, a,b,c,d,e,f,clk,clkdyn);
  output[5:0]   sa;
  output[7:0]   lsg;
  input[3:0]    a,b,c,d,e,f;
  input         clk,clkdyn;

  wire[7:0] dina,dinb,dinc,dind,dine,dinf;

  dynamic dn(sa, lsg, dina, dinb, dinc, dind, dine, dinf, clkdyn, clk);

  function [6:0] segmake;
  input[3:0]    cnt;
    case(cnt)
      4'd0:    segmake[6:0] = 7'b1000000;
      4'd1:    segmake[6:0] = 7'b1111001;
      4'd2:    segmake[6:0] = 7'b0100100;
      4'd3:    segmake[6:0] = 7'b0110000;
      4'd4:    segmake[6:0] = 7'b0011001;
      4'd5:    segmake[6:0] = 7'b0010010;
      4'd6:    segmake[6:0] = 7'b0000010;
      4'd7:    segmake[6:0] = 7'b1011000;
      4'd8:    segmake[6:0] = 7'b0000000;
      4'd9:    segmake[6:0] = 7'b0010000;
      4'd10:   segmake[6:0] = 7'b0001000;
      4'd11:   segmake[6:0] = 7'b0000011;
      4'd12:   segmake[6:0] = 7'b1110111;
      4'd13:   segmake[6:0] = 7'b1110000; //)
      4'd14:   segmake[6:0] = 7'b1000110; //(
      4'd15:   segmake[6:0] = 7'b0000110;
      default: segmake[6:0] = 7'b1111000;
    endcase
  endfunction   

  assign dinf = {1'b1, segmake( f )};
  assign dine = {1'b1, segmake( e )};
  assign dind = {1'b1, segmake( d )};
  assign dinc = {1'b0, segmake( c )};
  assign dinb = {1'b1, segmake( b )};
  assign dina = {1'b1, segmake( a )};

endmodule

module dynamic(sa, lsg, dina, dinb, dinc, dind, dine, dinf, clkdyn, clk);
  output[5:0]   sa;
  output[7:0]   lsg;
  reg[7:0]      lsg;
  input[7:0]    dina, dinb, dinc, dind, dine, dinf;
  input         clkdyn, clk;

  reg[3:0]  cnt;
  reg[5:0]  saen;

  // cnt move (dynamic cout)
  always @(posedge clkdyn)
  if(cnt >= 6)  cnt = 0;
  else      cnt = cnt + 1;
  
  // make anode(l active)
  always @(posedge clk)
  case(cnt)
    4'd0:    saen = 6'b111110;
    4'd1:    saen = 6'b111101;
    4'd2:    saen = 6'b111011;
    4'd3:    saen = 6'b110111;
    4'd4:    saen = 6'b101111;
    4'd5:    saen = 6'b011111;
    default: saen = 6'b111111;
  endcase

  assign sa[0] = (saen[0] == 0)? 0:1'bz;
  assign sa[1] = (saen[1] == 0)? 0:1'bz;
  assign sa[2] = (saen[2] == 0)? 0:1'bz;
  assign sa[3] = (saen[3] == 0)? 0:1'bz;
  assign sa[4] = (saen[4] == 0)? 0:1'bz;
  assign sa[5] = (saen[5] == 0)? 0:1'bz;
  
  // data selector
  always @(posedge clk)
  case(cnt)
    4'd0:    lsg = dina;
    4'd1:    lsg = dinb;
    4'd2:    lsg = dinc;
    4'd3:    lsg = dind;
    4'd4:    lsg = dine;
    4'd5:    lsg = dinf;
    default: lsg = 7'bxxxxxxx;
  endcase
endmodule


/*
   Turing Machine
   8symbol
   0: 0
   1: 1
   2: 2
   3: 3
   4: 4
   5: 5
   6: 6
   7: 7
   8: 8
   9: 9
   10: A
   11: B
   12: _
   13: )]}
   14: ([{
   15: E

*/

module tm(led5,led4,led3,led2,led1,led0,keypush,keyon,dclk,clk,rxd, txd);
  output[3:0]   led5,led4,led3,led2,led1,led0;
  input[3:0]    keypush,keyon;
  input         dclk,clk,rxd;
  output        txd;

  reg[6:0]      cnt;

  parameter ssize=4;
  parameter wsize=128;

  /*----- tape start ---*/
  reg[6:0]          position;
  reg[ssize-1:0]    tapebit[0:wsize-1]; //ssize bit 128word memory
  wire[ssize-1:0]   data;
  reg[ssize-1:0]    wdata;
  reg               wbit;
  reg               lbit;
  reg               rbit;
  assign data=tapebit[position];

  task shiftl;
    begin
      lbit=1;
    end
  endtask

  task shiftr;
    begin
      rbit=1;
    end
  endtask

  task write;
    input[ssize-1:0] d;
    begin
      wdata=d;
      wbit=1;
    end
  endtask
  task update;
    begin
      if(wbit==1)
      begin
        tapebit[position]=wdata;
      end
      if(lbit==1)
      begin
        position=position+1;
      end
      if(rbit==1)
      begin
        position=position-1;
      end
      wbit=0;
      lbit=0;
      rbit=0;
    end
  endtask
  /*----       end tape          ----*/


  /*-------------- rs232c -----------------*/
  wire       TX_EN, RX_EN, RDEN ;
  wire [7:0] ASCII;
  RS232C_CLKGEN U0( clk, RST, TX_EN, RX_EN );
  RS232C_RX     U1( clk, RST, RX_EN, rxd, ASCII, RDEN );
  RS232C_TX     U2( clk, RST, TX_EN, RDEN, ASCII, txd );

  /*--------------rs232c ---------------*/

  /*---- start turing machine ---*/
  parameter qsize=3;
  reg[qsize-1:0] state; //2bit state Q0,Q1,H
  function ifstate;
    input[qsize-1:0] s;
    input[ssize-1:0] r;
    begin
      ifstate = (state==s && r==data) ? 1'b1 : 1'b0;
    end
  endfunction

  task newstate;
    input[qsize-1:0] s;
    input[ssize-1:0] r;
    input m; // 1: right 0: left
    begin
      write(r);
      state=s;
      if(m==1) shiftr;
      else if(m==0) shiftl;
    end
  endtask
  
  task step;
    begin
    /* parity checker  */
    /*
    case({state,data})
    {3'd0,4'd0}: newstate(0,3,1);
    {3'd0,4'd1}: newstate(1,3,1);
    {3'd1,4'd0}: newstate(0,3,1);
    {3'd1,4'd1}: newstate(0,3,1);
    {3'd0,4'd2}: newstate(2,4,1);
    {3'd1,4'd2}: newstate(0,5,1);
    endcase
    *

    // () checker
    case({state,data})
    {3'd0,4'he}: newstate(0,4'he,1);
    {3'd0,4'hd}: newstate(1,4'hc,0);
    {3'd0,4'hf}: newstate(2,4'hf,0);
    {3'd0,4'hc}: newstate(0,4'hc,1);
    {3'd1,4'he}: newstate(0,4'hc,1);
    {3'd1,4'hd}: newstate(1,4'hd,0);
    {3'd1,4'hf}: newstate(6,4'h0,0);
    {3'd1,4'hc}: newstate(1,4'hc,0);
    {3'd2,4'he}: newstate(6,4'h0,0);
    {3'd2,4'hd}: newstate(6,4'hd,0);
    {3'd2,4'hf}: newstate(6,4'h1,0);
    {3'd2,4'hc}: newstate(2,4'hc,0);
    endcase   
    
    */
    case({state,data})
    {3'd0,4'h0}: newstate(0,4'h0,1);
    {3'd0,4'h1}: newstate(0,4'h1,1);
    {3'd0,4'hb}: newstate(0,4'hb,1);
    {3'd0,4'hf}: newstate(1,4'hf,0);
    {3'd0,4'ha}: newstate(4,4'ha,1);
    {3'd1,4'h0}: newstate(1,4'h0,0);
    {3'd1,4'h1}: newstate(2,4'ha,0);
    {3'd1,4'hb}: newstate(6,4'hb,0);
    {3'd2,4'h0}: newstate(2,4'h0,0);
    {3'd2,4'h1}: newstate(2,4'h1,0);
    {3'd2,4'hb}: newstate(3,4'hb,0);
    {3'd3,4'hc}: newstate(0,4'h1,1);
    {3'd3,4'h0}: newstate(0,4'h1,1);
    {3'd3,4'h1}: newstate(0,4'h2,1);
    {3'd3,4'h2}: newstate(0,4'h3,1);
    {3'd3,4'h3}: newstate(0,4'h4,1);
    {3'd3,4'h4}: newstate(0,4'h5,1);
    {3'd3,4'h5}: newstate(0,4'h6,1);
    {3'd3,4'h6}: newstate(0,4'h7,1);
    {3'd3,4'h7}: newstate(0,4'h8,1);
    {3'd3,4'h8}: newstate(0,4'h9,1);
    {3'd3,4'h9}: newstate(3,4'h0,0);
    {3'd4,4'h0}: newstate(4,4'h0,1);
    {3'd4,4'h1}: newstate(4,4'h1,1);
    {3'd4,4'hf}: newstate(5,4'hf,0);
    {3'd5,4'h0}: newstate(5,4'h1,0);
    {3'd5,4'h1}: newstate(5,4'h0,0);
    {3'd5,4'ha}: newstate(0,4'h0,0);
    endcase   
    //*/
    end
  endtask

  reg dclkedge;

  always@ (posedge clk)
  begin
    if(dclkedge==0 && dclk==1)
    begin
        if(keyon[3]==1)
        begin    
            cnt=cnt+1;
            if(cnt>=4)
            begin
                cnt=0;
                step;
            end
        end
        else
            cnt=0;
    end
    dclkedge=dclk;

    if(keypush[0]==1)
    begin
        write(data+1);
        state=0;
    end

    if(keypush[1]==1 && keypush[2]==0)
    begin
      shiftl;
      state=0;
    end

    if(keypush[2]==1 && keypush[1]==0)
    begin
      shiftr;
      state=0;
    end
    if(keyon[1]==1 && keyon[2]==1)
    begin
      state=0;
      position=0;
      write(1);
    end

    if(RDEN)
    begin
      case(ASCII)
        8'h30: write(0);
        8'h31: write(1);
        8'h32: write(2);
        8'h33: write(3);
        8'h34: write(4);
        8'h35: write(5);
        8'h36: write(6);
        8'h37: write(7);
        8'h38: write(8);
        8'h39: write(9);
        // A
        8'h41: write(10);
        8'h61: write(10);
        //B
        8'h42: write(11);
        8'h62: write(11);
        //)
        8'h29: write(13);
        8'h7d: write(13);
        8'h5d: write(13);
        //(
        8'h28: write(14);
        8'h7b: write(14);
        8'h5b: write(14);
        //E
        8'h45: write(15);
        8'h65: write(15);
        default: write(12);
      endcase
      shiftr;
    end

    update;
  end

  assign led5=tapebit[(position+3)&7'b1111111];
  assign led4=tapebit[(position+2)&7'b1111111];
  assign led3=tapebit[(position+1)&7'b1111111];
  assign led2=tapebit[position];
  assign led1=tapebit[(position-1)&7'b1111111];
  assign led0=tapebit[(position-2)&7'b1111111];

endmodule

module showtm(sa,lsg,clk,clkdyn, led5,led4,led3,led2,led1,led0);
  input         clk, clkdyn;
  input[3:0]    led5,led4,led3,led2,led1,led0;
  output[7:0]   lsg;
  output[5:0]   sa;

  wire[3:0]  cnt0, cnt1, cnt2, cnt3, cnt4, cnt5;

  dynamic_7seg dn(sa, lsg, cnt0,cnt1,cnt2,cnt3,cnt4,cnt5,clk,clkdyn);

  assign cnt0=led0;
  assign cnt1=led1;
  assign cnt2=led2;
  assign cnt3=led3;
  assign cnt4=led4;
  assign cnt5=led5;

endmodule